FPGA Implementation of High-Dependability RISC-V Processor System

Contracting organization: 国立大学法人東京工業大学

1. Items Subject to Bidding(1) Classification Number: 71(2) Subject and Quantity: FPGA Implementation of High-Dependability RISC-V Processor System, 1 set(3) Specifications: As per the tender documentation.(4) Performance Period: From September 4, 2026, to March 31, 2027.(5) Performance Location: Institute of Science Tokyo, Ookayama Campus.(6) Bidding Method: The contract price will be the amount stated in the bid plus 10 percent (consumption tax and local consumption tax). Bidders must submit their bids based on the amount excluding tax (100/110 of the total estimated contract value).2. Elig…